1. Field of the Invention
Example embodiments of the present invention relate generally to a multi-port semiconductor device and method thereof.
2. Description of the Related Art
A multi-port memory device may include a plurality of ports that may be used in conjunction with a plurality of applications.
FIG. 1 is a block diagram illustrating a conventional multi-port memory device. Referring to FIG. 1, the multi-port memory device 100 may include a memory core 110 having memory banks 111, 112 and 113 and ports 120, 130, 140 and 150. The port 120 may provide data DQ1 received from an external device to the memory core 110 and/or may output data that stored in the memory core 110 to an external device in response to a first external clock signal CLK1, an address signal ADDR1 and a command signal CMD1. The port 130 may provide data DQ2 received from an external device to the memory core 110 and/or may output data stored in the memory core 110 to an external device in response to a second external clock signal CLK2, an address signal ADDR2 and a command signal CMD2. The port 140 may provide data DQ3 received from an external device to the memory core 110 and/or may output data stored in the memory core 110 to an external device in response to a third external clock signal CLK3, an address signal ADDR3 and a command signal CMD3. The port 150 may provide data DQ4 received from an external device to the memory core 110 and/or may output data stored in the memory core 110 to an external device in response to a fourth external clock signal CLK4, an address signal ADDR4 and a command signal CMD4.
FIG. 2 is a block diagram illustrating another conventional multi-port memory device. Referring to FIG. 2, the multi-port memory device 200 may include a memory core 210 having memory banks 211, 212 and 213, ports 220, 230, 240 and 250 and a clock generator 255. The clock generator 255 may generate an internal clock signal ICLK based on an external clock signal CLK. The port 220 may provide data DQ1 received from an external device to the memory core 210 and/or may output data stored in the memory core 210 to an external device in response to the internal clock signal ICLK, an address signal ADDR1 and a command signal CMD1. The port 230 may provide data DQ2 received from an external device to the memory core 210 and/or may output data stored in the memory core 210 to an external device in response to the internal clock signal ICLK, an address signal ADDR2 and a command signal CMD2. The port 240 may provide data DQ3 received from an external device to the memory core 210 and/or may output data stored in the memory core 210 to an external device in response to the internal clock signal ICLK, an address signal ADDR3 and a command signal CMD3. The port 250 may provide data DQ received from an external device to the memory core 210 and/or may output data stored in the memory core 210 to an external device in response to the internal clock signal ICLK, an address signal ADDR4 and a command signal CMD4.
Referring to FIG. 2, the port (PORT1) 220 may receive an address signal ADDR1 and a command signal CMD1 from the host (HOST1) 260, and may receive and transmit data DQ1 to and from the host (HOST1) 260. The port (PORT2) 230 may receive an address signal ADDR2 and a command signal CMD2 from the host (HOST2) 270, and may receive and transmit data DQ2 to and from the host (HOST2) 270. The port (PORT3) 240 may receive an address signal ADDR3 and a command signal CMD3 from the host (HOST3) 280, and may receive and transmit data DQ3 to and from the host (HOST3) 280. The port (PORT4) 250 may receive an address signal ADDR4 and a command signal CMD4 from the host (HOST4) 290, and may receive and transmit data DQ4 to and from the host (HOST4) 290.
In the conventional multi-port memory device 100 shown in FIG. 1, each of the ports 120, 130, 140 and 150 may operate in response to one of a plurality of clock signals CLK1, CLK2, CLK3 and CLK4 having different frequencies received from external devices. Accordingly, the multi-port memory device 100 of FIG. 1 may include pins on which to receive the clock signals CLK1, CLK2, CLK3 and CLK4, respectively, from the external devices.
In the conventional multi-port memory device 200 shown in FIG. 2, each of the ports 220, 230, 240 and 250 may operate in response to the internal clock signal ICLK (e.g., a single, internally generated clock signal). Accordingly, the multi-port memory device 200 may not be adaptable to hosts operating at different frequencies because the same clock signal is used at each of the ports 220, 230, 240 and 250, whereas the multi-port memory device 100 of FIG. 1 may be dependent upon a plurality of external devices to generate the different frequencies of the clock signals for one or more associated hosts.